DfX (Design for X)

This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems s uch as automobiles, aircrafts, or medical equipments would not allow an y interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure predicti on technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliabilit y in the field, the proposed technique should take into consideration va rious types of aging mechanisms and the testing environment of voltag e and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement techniqueconsidering the variation due to voltage and temperature and 2) an adaptive tes t scheduling that gives more test chances to more probable degrad ing parts. Experimental results show the required memory space and area cost for implementing the proposed technique.

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than fu nctional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existin g at-speed test clock control methods and present an on-chip faster-t han-at-speed test clock control scheme for intra/inter-clock domain tes t. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method en ables faster-than-at-speed test of SoCs with multiple clock dom ains.

본 논문은 FPGA 내부의 경계 스캔 체인을 자가 테스트 회로로써 재활용하기 위한 FPGA 자가 테스트 회로 설계 기술을 소개한다. FPGA의 경계 스캔 체인은 테스트나 디버깅 기능뿐만 아니라 각 셀에 연결되어 있는 입출 력 핀의 기능을 설정하기 위해서도 사용되기 때��일반적인 칩의 경계 스캔 셀보다 매우 크다. 따라서, 본 논문에서는 FPGA 경계 스캔 셀의 구조 를 분석하고 소수의 FPGA 로직�함께 테스트 패턴 생성과 결과 분석이 가능하도록 설계한 BIST(built-in-self-test) 회로를 제시한다. FPG A의 경계 스캔 체인�자가 테스트를 위하여 재사용함으로써 면적 오버헤드를 줄일 수 있고 보드상에서 프로세서를 사용한 온-라인(on-line) 테스트/모니 터링도 가능하다. 실험을 통하여 오버헤드 증가량과 시뮬레이션 결과를 제 시한다.