콘텐츠 본문
논문 해외 국제전문학술지(SCI급) A FAILURE PREDICTION STRATEGY FOR TRANSISTOR AGING
- 학술지 구분 국제전문학술지(SCI급)
- 게재년월 2012-11
- 저자명 이현빈
- 학술지명 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- 발행처명 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행국가 해외
- 논문언어 외국어
- 전체저자수 6
논문 초록 (Abstract)
This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems s uch as automobiles, aircrafts, or medical equipments would not allow an y interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure predicti on technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliabilit y in the field, the proposed technique should take into consideration va rious types of aging mechanisms and the testing environment of voltag e and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement techniqueconsidering the variation due to voltage and temperature and 2) an adaptive tes t scheduling that gives more test chances to more probable degrad ing parts. Experimental results show the required memory space and area cost for implementing the proposed technique.
