콘텐츠 본문
논문 해외 국제전문학술지(SCI급) AN ON-CHIP TEST CLOCK CONTROL SCHEME FOR CIRCUIT AGING MONITORING
- 학술지 구분 국제전문학술지(SCI급)
- 게재년월 2013-02
- 저자명 이현빈
- 학술지명 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- 발행처명 IEEK PUBLICATION CENTER
- 발행국가 해외
- 논문언어 외국어
- 전체저자수 1
논문 초록 (Abstract)
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than fu nctional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existin g at-speed test clock control methods and present an on-chip faster-t han-at-speed test clock control scheme for intra/inter-clock domain tes t. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method en ables faster-than-at-speed test of SoCs with multiple clock dom ains.
