Circuits for Analog Tolerant Systems Lab.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator, and a clocked comparator is followed for quantization. Without any continuous-time feedback circuit, the converter performs a first-order noise shaping of the quantization error. In order to minimize static power consumption, the proposed circuit employs a single-ended current-steering digital-to-analog converter which flows only the same current as the input. By adopting a switching noise averaging algorithm, our dynamic element matching not only mitigates mismatch of current sources in the current-steering DAC, but also makes the effect of dynamic switching noise become an input-independent constant. The implemented circuit in 0.35 mu m CMOS converts the current input with a range of 2.8 mu A to 15b digital output in about 4 ms, showing a DNL of + 0.24/ - 0.25 LSB and an INL of + 1.98/ - 1.98 LSB while consuming 16.8 mu W.

This paper presents detailed analyses on leakage-based bandgap reference (BGR) circuit for ultralow-power applications. Design considerations for power supply rejection ratio and noise characteristics are provided with pole/zero analysis. Startup settling issue is also discussed with measurements. For verification, a test BGR circuit is implemented in a 0.18-mu m CMOS technology. The standard deviation of proportional-toabsolute-temperature (PTAT) voltages measured from 20 chips is 1.15% at 30 degrees C. The BGR also uses two PTAT voltages to reduce the resistance for complementary-to-absolute-temperature generation, hence alleviating the tradeoff limitation between power consumption and area cost. With an active area of 0.056 mm(2), the BGR consumes 19 nW at room temperature. Measurements from 20 chips show a standard deviation of 0.54% at 30 degrees C without any trimming, a temperature dependence of 143 ppm/degrees C and a line regulation of 2.4%/V.

This article presents a methodology to design a circuit to compensate for process skew by exploiting an inherent dimension-dependent effect of process skew on change in the threshold voltage. We design a voltage reference circuit with a hybrid architecture of bandgap reference (BGR) and CMOS reference, which generates a nominal voltage level of (bandgap - threshold). By compensating the process skew of the threshold term with the proposed dimension-induced effect as well as the temperature dependence, the circuit achieves the simultaneous benefits of BGR and CMOS references. For verification, the circuit was fabricated in three wafers of a 0.18-mu m CMOS including extreme slow and fast corners. With an active area of 0.0045 mm(2), it consumes 192 pW at room temperature. Measurement from 45 chips (15 chips per wafer) shows untrimmed process/voltage/temperature variations of 0.53%, 0.020%/V, and 33 ppm/degrees C, respectively.