콘텐츠 본문
논문 해외 국제전문학술지(SCI급) Dual Strategy of Electroless Metal Deposition and Surface Silylation toward Scalable Low-temperature Hybrid Bonding for Advanced Packaging Applications
- 학술지 구분 국제전문학술지(SCI급)
- 게재년월 2025-06
- 저자명 Otgonbayar, Z., Kim, J. H., Rho, J., Kim, J.-C., Noh, J., Kim, J.,* Yoon, S.-H.,* and Yoon C.-M.*
- 학술지명 IEEE Access
- 발행국가 해외
- 논문언어 외국어
- 전체저자수 8
논문 초록 (Abstract)
The growing demand for high-performance computing and compact electronics has driven the transition toward advanced three-dimensional (3D) packaging technologies. Traditional packaging technologies, such as micro-bump interconnections, face limitations in achieving sub-micrometer pitches, prompting the development of alternative bonding strategies. Among them, Cu/SiO2 hybrid bonding (HB) has emerged as a promising method for enabling fine-pitch, high-density interconnects in next-generation semiconductor packaging. In this study, a reliable low-temperature Cu/SiO2 HB process was developed by combining electroless gold deposition (ELD) on Cu pads with selective surface functionalization of the SiO2 dielectric using silane. The ELD process facilitated uniform and selective Au deposition on Cu, acting as a diffusion metal that maintained interfacial stability during bonding. Conclusively, the SiO2 surface was modified with (3-aminopropyl)triethoxysilane (APTES), which formed strong covalent networks through silane polymerization, enhancing adhesion at the dielectric interface. This dual-modification strategy facilitated direct Cu–Cu bonding and robust SiO2–SiO2 adhesion, resulting in a defect-free interface without voids or delamination. The bonding was conducted at a low-temperature of 250 °C, thereby minimizing thermal stress typically associated with conventional high-temperature bonding processes. These result clearly demonstrates a practical and scalable method for achieving low-temperature Cu/SiO2 HB, contributing to the advancement of 3D integration in semiconductor packaging.
