콘텐츠 본문
논문 해외 국제전문학술지(SCI급) Ultrathin sputtered IZO overlayer engineering for high-performance solution-processed oxide TFTs
- 학술지 구분 국제전문학술지(SCI급)
- 게재년월 2026-12
- 저자명 Changmin An1, Tae Kyu Nam1, Hyeon Seok Bae, Sang-Eun Bae, Yo-Han Seo, Dong-Wook Shin*, Jong Beom Ko*
- 학술지명 Materials Science in Semiconductor Processing
- 발행처명 ELSEVIER
- 발행국가 해외
- 논문언어 외국어
- 전체저자수 7
- 논문 다운로드 링크(외부) https://doi.org/10.1016/j.mssp.2026.111099
- 연구분야 공학 > 재료공학
- 키워드 #thin-film devices #semiconductor #backplane #thin-film transistors
논문 초록 (Abstract)
We report an IZO bilayer channel architecture for high-performance oxide thin-film transistors (TFTs), where the thickness of the ultrathin sputtered IZO layer on the solution-processed IZO is utilized to control film morphology, carrier transport, and turn-on voltage behavior. A solution-processed IZO bottom layer was fixed at approximately 10 nm, followed by the sputtered IZO overlayer, which was systematically varied from 3 to 5 nm. The addition of the ultrathin sputtered IZO layer significantly improved the electrical properties of the solution-processed IZO TFTs by modulating film morphology and carrier transport behavior. Power-law mobility analysis revealed that the 3 nm bilayer device remains governed by trap-limited conduction, whereas the 4 and 5 nm bilayer devices undergo a gate-field-induced transition from trap-limited conduction to percolation conduction. This transition is attributed to the formation of an interface-assisted percolation pathway around the buried solution IZO/sputtered IZO interface. An optimized 4 nm sputtered IZO overlayer provides the best-balanced performance, including near-zero turn-on voltage, improved switching behavior, mobility enhancement, and gate-voltage controllability, which offers a practical route for high-performance solution-processed oxide TFTs.
